1. Field of the Invention
The present invention relates to a semiconductor gate array and, more particularly, to an arrangement of cells and interconnection structure among cells.
2. Description of the Prior Art
Generally, the gate array is defined on a rectangular LSI chip having I/O (input and output) cells aligned along the four peripheral sides of the chip and a certain number of basic cells aligned in a number of rows and in an area surrounded by I/O cells.
An example of a prior art gate array is shown in FIG. 1a. Basic cells 1, each serving as a transistor, diode or any other electronic element, are aligned side-by-side in a row 10, and there are a plurality of, such as eight as shown in FIG. 1a, rows aligned parallelly to each other with a predetermined space W (FIG. 1b) between adjacent rows 10. Provided around the basic cell rows and along the four sides of a rectangular semiconductor chip are I/O cells 2 each having a width M and includes a certain number of transistors. Each I/O cell 2 has a power source terminal PDD and a ground terminal PSS for the electric power supply to each active basic cell 1. From power terminal PDD and ground terminal PSS of each I/O cell 2, power line VDD and ground line VSS extend parallel with one another and cross the row of basic cells 1 longitudinally, as shown in FIG. 1b.
In the drawing, a circle dot indicates an electric contact at which the line VDD or VSS is connected to the basic cell. Generally, the semiconductor chip has a multi-layer structure, and therefore, the line VDD or VSS is formed at a level different from the level provided with the cells. Accordingly, the contacts indicated by the circle dots extend in the thickness direction of the semiconductor chip. For example, in FIG. 1b, basic cell 1a is connected to lines VDD and VSS through power contact D and ground contact S. Similarly, basic cells 1c, 1e and 1f are connected to lines VDD and VSS through contacts D and S. The electric connection among basic cells and I/O cells for the signal transmission is done by a number of parallel lines (not shown) extending in the space W and also in a space between the edge of rows and the I/O cells.
According to the prior art gate array, since lines VDD and VSS extend from terminals PDD and PSS straight and parallel with one another, and cross the corresponding basic cell row longitudinally, the pitch between the rows 10 is equal to the pitch of the I/O cells 2. Accordingly, when designing various types of gate arrays, the percentage of the dead space occupied in one chip becomes relatively high, as explained below.
For example, when the number of the rows is made greater than the number of I/O cells aligned perpendicular to the rows, i.e., vertically when viewed in FIG. 1a, the I/O cells can be aligned with no extra space therebetween, but there may be some extra space between the rows aligned in alignment with each vertically aligned I/O cells, such as in the case when the number of signal transmission lines to be extended between the rows is rather small.
On the other hand, when the number of rows is made less than the vertically aligned I/O cells and, at the same time, the space W is widened, as shown in FIG. 2, for the reason such as to incorporate a greater number of signal transmission lines in the space W or for other reasons, the pitch of the I/O cells is also widened, requiring an unnecessary extra space X between I/O cells.
Also, according to the prior art gate array, within the width M (upper portion of FIG. 1a) of one I/O cell aligned parallel to the basic cell rows, there are exactly N (N being an integer) basic cells, and in the example shown in FIG. 1a, there are three basic cells included within the width M.
In other words, according to the prior art gate array, there is a correlation between the pitch of I/O cells and the pitch of basic cell rows, and also a correlation between the pitch of I/O cells and the pitch of basic cells in the row. Such a correlation will restrict the designing of various different arrangements of gate arrays, such as a semi-custom type gate array. The semi-custom type is a ready made type having basic cells and I/O cells already aligned on a master chip, but no lines and no contacts are provided. Later, in accordance with the customer's request, the lines and contacts designed in a particular pattern are added to complete the logic circuit as required by the customer. To meet the wide use, the gate array of semi-custom type may have a long pitch between the rows for allowing a great number of transmission lines between the rows and, at the same time, a great number of I/O cells for the wide use. However, because of the correlation between the pitch of I/O cells and the pitch of basic cell rows or basic cells described above, it has been very difficult to minimize the size of the chip for the given number of cells.